Jordan T. Wyckoff
OBJECTIVE:
To continue to expand my knowledge and experience in the field of Computer/Electrical Engineering and related fields as well as excel in innovative circuit design and interact and share with team members and colleagues.
EXPERIENCE:
March 2008 present Nanya Technology Corporation Delaware
Burlington, VT
Design/Physical Design Engineer
Lead physical design coordinator for multiple low power DRAM memory projects used in mobile applications.
Responsible for chip level floor planning and partitioning
Floor planned power system at macro level for a regulated low power design.
Created custom physical design for multiple power amps and regulators at the transistor level.
Implemented power grid analysis for I/R drop
Performed all final verification checks for physical data tape out, using both Calibre and Hercules verification tools (LVS, DRC, antenna, etc)
Experience with GDSII data stream and submission to fabrication site for mask generation
Interaction with OPC team based in Taiwan for post processing optimization
Generated physical design for DRAM core memory cells using automated core builder routines. Requires understanding and manipulation of Perl script routines and parameter settings.
Responsible for mask design of low power DRAM memory array as well as interfacing logic for data read and write. Required extensive interaction with processing engineers based in Taiwan due to recent technology migration.
Participated in training courses for Laker APR tool.
Responsible for full chip verilog verification and debug on 1GB low power mobile DRAM design
Generated verilog patterns for common DRAM routines (i.e. activate. read, write, repair)
Extensive verilog verification and debug of DRAM data transfer and address allocation using multiple configurations
Executed hspice simulations of digital circuitry
Produced netlist to GDSII implementation of digital circuitry at both core and macro level
March 2007 Jan. 2008 Qimonda
Williston, VT
Physical Design Engineer
Responsible for mask design on multiple DRAM chips
Custom layout of periphery circuits and some analog blocks using Cadence Virtuoso, verification checks using Assura and Calibre (LVS, DRC, Antenna)
Participated in training courses for Cadence VXL and Pulsic Lyric router tools.
Involvement with global wiring allocation and block level floor planning
Mentored by layout coordinator on chip level verifications and final tape out procedures
June - Dec. 2006 NOVA Technical Corporation
Portsmouth, NH
Engineering Intern
Interned with R&D team during system validation phase of a non-invasive health monitoring system for the military
Designed/programmed multiple drivers using MPLAB IDE for PIC microcontroller
Developed data transfer protocols between microcontrollers (PXA PIC)
Desig...
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