Skill Summary
• 5 years plus Hands-on experience on ASIC, FPGA, Analog/Digital circuits design, Schematic design, and Layout Verification
• 6 years plus experience with lab electronic hardware test equipments including Multimeter, Oscilloscope
• Familiar with ASIC Flow Design: Idea, Structural and Functional Description, RTL(Using Verilog or VHDL), Logic/RTL synthesis(Using Synopsys or Cadence tools), Layout and Verification
• Familiar with Wireless/Mobile Communications principles: Sampling, Quantizing, Source/Channel coding, Viterbi decoding algorithm, Modulation/Detection (B/QPSK/QAM), Radio propagation model, Cellular fundamental, F/T/CDMA, IEEE 802.11 series standards etc.
• Familiar with circuit optimization schemes: Pipelining/Parallel Processing, Retiming, Folding/Unfolding, Transposition, Numerical Strength Reduction with Subexpression Elimination and CSD (Canonical Signed Digit) etc.
• Tools: Cadence, Synopsys, Xillinx, Modelsim, Hspice, Magic, Gemini, MS Office
• Computer languages and system: C/C++, Perl, Verilog, VHDL, , Matlab; Windows, Unix(Solaris), Linux(Fedora and Ubuntu)
• Excellent analytical and communication skills
Working Experience
Beijing Toplink Communication LLC. , Hardware Engineer, Aug 2004 – Aug 2007
Job Duty: Develop Hardware for Spread Spectrum Microwave communication devices and components.
Exchanger B10 Project, Aug 2004 – Feb 2005.
Design and analysis a 2-stage Operational Amplifier
By using 8 CMOS transistor to implement a two-stage Op Amp, the Open Loop Gain, Phase Margin, Gain Margin get the expect results.
Spread Spectrum Communication System Project, March 2005 – Aug 2007.
Design and Analyze 16-bit Zero-Aware (ZA) Asymmetric SRAM
Dual-Vt technology is employed in this project. Since there is no precharge on write “0” mode, compared to the traditional 6T SRAM, the ZA SRAM can save 90% power on write mode, 40% power on read mode.
Design and analyze (delay, area, power) 1-bit, 8bit, and 32-bit latch-free Bus Specific Clock Gating (BSCG) Register
Modelsim is employed to debug and compile Verilog files, then Formality is to check the functionality and Hpsice is to simulate. The BSCG can save 40% power consumption compared to the non-clock gating design.
Beijing Toplink Communication LLC. , Field Engineer, Sept 2007 – Oct 2009
Jop Duty: Provide on-site technical supports to clients(China Mobile Communication Company and China Unicom Communication Company), such like Install and Relocate Spread Spectrum Microwave system in Base Station; Analyze and Optimize the quality of transmission signals, by adjusting the antenna angle, check the connection with Switch and worn-out cables, and so on.
Project Experience
ASIC-BASED Design, Synthesis and validate 32-bit Carry-Look-Ahead CPU using Verilog
Aug 2010 to Dec 2010
The whole project includes Schematic design (Memory, ALU, Control component, Program Counter, ROM, BUS, etc.), Verilog programming, Design Validation (observe the waveform in Cadence SimVision), Synthesis (RTL simulation, Post-Synthesis simulation, Post-Place&Route simulation(Cadence SOC Encounter), Layout-Versus-Schematic verification(Gemini).
Design and analyze power consumption of three patterns of 4-bit Full Adders
Jan 2011 to May2011
There are three scenarios, high-Vt, dual-Vt with standby mode, and Dual-Vt + Standby mode and sleep switches. Employed Cadence IC 6.1 tools (schematic), Hspice (simulation) and Synopsys Nanosim (power analysis).
Discrete Fourier Transform Implementations based on Goertzel, Cooley-Tukey and Rader algorithms using Matlab to design and VHDL to synthesis Jan 2012 to May 2012
C language design and comparison power analysis on 5 sorting algorithm: Heap, Insert, Merge, Shell, Selection; Digital logic simulation language built by C++, including Lexical Analysis, Syntactic Analysis, Netlist Construction and Logic Simulation Jan 2011 to May 2011
32-bit MIPS processor design by utilizing VHDL Aug 2011 to Dec 2011
Contains the design of CPU, Bus, Cache, ISA, Memory and Instructions.
Curriculum Vitae
Introduction to VLSI Design
Processing, fabrication, and design of Very Large Scale Integration (VLSI) circuits. MOS transistor theory, VLSI processing, circuit layout, layout design rules, layout analysis, and performance estimation. The use of computer aided design (CAD) tools for layout design, system design in VLSI, and application-specific integrated circuits (ASICs).
Advanced VLSI Systems Design
ASIC Design tools and techniques, clocking issues, complexity management, layout and floor planning, array structures, testing and testability, advanced arithmetic circuitry, transcendental function approximations, architectural issues, signal processing architecture and sub-micron design.
Digital System-On-Chip Design
Digital design techniques and hardware/software realization concepts in embedded computing systems using VHDL. Topics include: basics principles of VHDL programming; designing with FPGA; design of arithmetic logic unit; VHDL models for memories and busses; CPU design; system-on-chip design; efficient hardware realizations of FFT, DCT, and DWT.
High Performance V...
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